diff options
| author | Bhanu Prakash Maiya <bhanumaiya@google.com> | 2021-08-10 15:58:58 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-13 18:03:40 +0000 |
| commit | adc9e63c59829dba78888914c740a7dbf073508d (patch) | |
| tree | f66c4f772655ebe32fdb327ea8be9e0ab300e3c6 /util/mainboard/google/guybrush/template | |
| parent | eb32a85ade2cd85a9311b7888f0e848c7d8299f6 (diff) | |
util/mb/google: add template files for guybrush
Create template for guyrbsuh variant creation.
BRANCH=none
BUG=b:194031783
TEST=n/a
Change-Id: If62c1a63d0890539d4b43f840f75ee9d7ceab4f8
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'util/mainboard/google/guybrush/template')
7 files changed, 33 insertions, 0 deletions
diff --git a/util/mainboard/google/guybrush/template/Makefile.inc b/util/mainboard/google/guybrush/template/Makefile.inc new file mode 100644 index 0000000000..88e75bde52 --- /dev/null +++ b/util/mainboard/google/guybrush/template/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./memory diff --git a/util/mainboard/google/guybrush/template/include/variant/ec.h b/util/mainboard/google/guybrush/template/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/util/mainboard/google/guybrush/template/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/util/mainboard/google/guybrush/template/include/variant/gpio.h b/util/mainboard/google/guybrush/template/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/util/mainboard/google/guybrush/template/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/util/mainboard/google/guybrush/template/memory/Makefile.inc b/util/mainboard/google/guybrush/template/memory/Makefile.inc new file mode 100644 index 0000000000..b0ca2223a8 --- /dev/null +++ b/util/mainboard/google/guybrush/template/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/util/mainboard/google/guybrush/template/memory/dram_id.generated.txt b/util/mainboard/google/guybrush/template/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/util/mainboard/google/guybrush/template/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/util/mainboard/google/guybrush/template/memory/mem_parts_used.txt b/util/mainboard/google/guybrush/template/memory/mem_parts_used.txt new file mode 100644 index 0000000000..8124e4f7ed --- /dev/null +++ b/util/mainboard/google/guybrush/template/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) diff --git a/util/mainboard/google/guybrush/template/overridetree.cb b/util/mainboard/google/guybrush/template/overridetree.cb new file mode 100644 index 0000000000..c182265075 --- /dev/null +++ b/util/mainboard/google/guybrush/template/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/cezanne + device domain 0 on + + end # domain +end # chip soc/amd/cezanne |