rockchip/rk3399: Change 933 DPLL to low jitter rate

This changes the 933 DPLL rate to 928 which has low jitter.

BRANCH=none
BUG=chrome-os-partner:57845
TEST=boot kevin and run
while true; do sleep 0.1; memtester 500K 1 > /dev/null; done
for several hours

Change-Id: I4d2a8871aaabe3b0a1a165c788af265c5f9e892c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 54ebf8763bb8193c4b36a5e86f0c625b176d31a6
Original-Change-Id: Iaa12bf67527b6d0e809657c513b8d1c66af25174
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/404550
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17379
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

0 files changed, 0 insertions, 0 deletions