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authorSean Rhodes <sean@starlabs.systems>2024-07-18 21:08:30 +0100
committerSean Rhodes <sean@starlabs.systems>2024-10-11 08:31:52 +0000
commit1d535eb467c3a9119ec3022494ded8b06bf7ab28 (patch)
tree3671cd54be0daa7ad25658e3f9b34b3ca84eb842 /util/lint/lint-stable-005-board-status
parent9394bace4e798197414bc8e05be0bcbc0a767fe7 (diff)
soc/intel/cnvi: Add _S0W to ensure CNVi isn't put into D3 Cold
All CNVi modules, integrated or dedicated only support D3 Hot so add _S0W to limit the sleep state. Intel document #559910 details this. Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Diffstat (limited to 'util/lint/lint-stable-005-board-status')
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