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authorAngel Pons <th3fanbus@gmail.com>2020-11-02 12:13:23 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-18 10:10:13 +0000
commit9b629ad37f2fa9ceda61e2b18bc53f69833235c1 (patch)
treeb411a5ba092de22f158fe7bb2943e9d67d6a0759 /util/kconfig
parentea9c96aa9cc41234c99092ed13b536f6cb77ce22 (diff)
sb/intel/lynxpoint: Correct read width in RMW cycle
The register is 32 bits wide, so do not read 16 bits out of it. LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses. Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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