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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2019-03-13 18:16:01 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-03-18 09:18:18 +0000
commitbfe4a59bc97d086dc5152e5e082caaa09740aef6 (patch)
tree551438880b1b7d347aa81a8fb8eeb4ad651e7456 /util/intelvbttool
parent0f681dc5e63564aa50415723cee4b4ae831c2a30 (diff)
soc/intel/cannonlake: Pass coreboot debug interface info to FSP
coreboot have an option to use legacy UART or LPSS UART. FSP will use the UART initialized by coreboot and we can choose an option to skip Uart initialization by FSP. For this, we need to pass correct debug interface flag to FSP through which FSP will know which UART port to use. If we don't pass correct interface information, FSP may try to dump logs on that port and it may slow down the system. BUG=none BRANCH=none TEST=Compile and boot with coreboot. Check FSP and coreboot logs are coming on serial port. Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'util/intelvbttool')
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