nb/amd/mct_ddr3: Disable MCE framework during DRAM training

On Family 15h processors, with certain RDIMMs, MCEs are generated
as a normal part of DCT startup / DRAM training.  Disable sync
flood on parity or UC data error until ECC has been enabled.

Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14186
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

0 files changed, 0 insertions, 0 deletions