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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2017-06-09 14:07:20 +0200
committerMartin Roth <martinroth@google.com>2017-06-12 04:26:34 +0200
commit035cf718229baaa7cd412824d32501b1a9d55e1d (patch)
tree18dcb99c558c65443825fd28b9987c0860e9ee55 /util/inteltool
parentccc5513bd746ebb27f9044ed1200edd1379fa406 (diff)
mb/emulation/spike-riscv: Update UART address
I updated my spike patch[1] to cleanly apply to current spike master. As a side effect, the UART is now at 0x02100000. [1]: https://github.com/riscv/riscv-isa-sim/pull/53 Change-Id: I4cb09014619e230011486fa57636abe183baa4be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/20126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'util/inteltool')
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