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authorCorey Osgood <corey.osgood@gmail.com>2010-08-17 08:33:44 +0000
committerStefan Reinauer <stepan@openbios.org>2010-08-17 08:33:44 +0000
commitf366ce05ef3eb95c6c9d84a97cde1a4026f22787 (patch)
tree87733a7ba137fc9713fb96c2655ff6eef1a21e6f /util/inteltool/powermgt.c
parente7b7ae23e688fb883003aed42f614bcfa977894e (diff)
Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
Both are tested and appear to be working, however I'm not 100% clear on if the NM10 has any other PCI IDs. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/inteltool/powermgt.c')
-rw-r--r--util/inteltool/powermgt.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index f7275843f1..5f938353ee 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -477,6 +477,7 @@ int print_pmbase(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
+ case PCI_DEVICE_ID_INTEL_NM10:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich7_pm_registers;
size = ARRAY_SIZE(ich7_pm_registers);
@@ -491,6 +492,7 @@ int print_pmbase(struct pci_dev *sb)
pm_registers = ich9_pm_registers;
size = ARRAY_SIZE(ich9_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH8:
case PCI_DEVICE_ID_INTEL_ICH8M:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich8_pm_registers;