Added support to ICH9 chipset family

Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 94 insertions, 23 deletions

diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index ee0f485958..de28d6a6d3 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -21,47 +21,47 @@
 #include <stdio.h>
 #include "inteltool.h"
 
-static const io_register_t ich7_pm_registers[] = {
-	{ 0x00, 2, "PM1_STS" },
-	{ 0x02, 2, "PM1_EN" },
-	{ 0x04, 4, "PM1_CNT" },
-	{ 0x08, 4, "PM1_TMR" },
+static const io_register_t ich9_pm_registers[] = {
+	{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
+	{ 0x02, 2, "PM1_EN" },  // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
+	{ 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
+	{ 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
 	{ 0x0c, 4, "RESERVED" },
-	{ 0x10, 4, "PROC_CNT" },
+	{ 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK
 #if DANGEROUS_REGISTERS
 	/* These registers return 0 on read, but reading them may cause
-	 * the system to enter C2/C3/C4 state, which might hang the system.
+	 * the system to enter Cx states, which might hang the system.
 	 */
-	{ 0x14, 1, "LV2 (Mobile/Ultra Mobile)" },
-	{ 0x15, 1, "LV3 (Mobile/Ultra Mobile)" },
-	{ 0x16, 1, "LV4 (Mobile/Ultra Mobile)" },
+	{ 0x14, 1, "LV2 (Mobile)" },
+	{ 0x15, 1, "LV3 (Mobile)" },
+	{ 0x16, 1, "LV4 (Mobile)" },
+	{ 0x17, 1, "LV5 (Mobile)" },
+	{ 0x18, 1, "LV6 (Mobile)" },
 #endif
-	{ 0x17, 1, "RESERVED" },
-	{ 0x18, 4, "RESERVED" },
+	{ 0x19, 1, "RESERVED" },
+	{ 0x1a, 2, "RESERVED" },
 	{ 0x1c, 4, "RESERVED" },
-	{ 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" },
-	{ 0x21, 1, "RESERVED" },
-	{ 0x22, 2, "RESERVED" },
-	{ 0x24, 4, "RESERVED" },
-	{ 0x28, 4, "GPE0_STS" },
-	{ 0x2C, 4, "GPE0_EN" },
+	{ 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
+	{ 0x2C, 4, "GPE0_EN" },  // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
 	{ 0x30, 4, "SMI_EN" },
 	{ 0x34, 4, "SMI_STS" },
 	{ 0x38, 2, "ALT_GP_SMI_EN" },
 	{ 0x3a, 2, "ALT_GP_SMI_STS" },
-	{ 0x3c, 4, "RESERVED" },
+	{ 0x3c, 1, "UPRWC" },   // USB Per-Port registers write control;
+	{ 0x3d, 2, "RESERVED" },
+	{ 0x3f, 1, "RESERVED" },
 	{ 0x40, 2, "RESERVED" },
 	{ 0x42, 1, "GPE_CNTL" },
 	{ 0x43, 1, "RESERVED" },
-	{ 0x44, 2, "DEVACT_STS" },
+	{ 0x44, 2, "DEVACT_STS" }, // Device Activity Status
 	{ 0x46, 2, "RESERVED" },
 	{ 0x48, 4, "RESERVED" },
 	{ 0x4c, 4, "RESERVED" },
-	{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
+	{ 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK
 	{ 0x51, 1, "RESERVED" },
 	{ 0x52, 2, "RESERVED" },
-	{ 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" },
-	{ 0x58, 4, "RESERVED" },
+	{ 0x54, 4, "C3_RES (Mobile)" },
+	{ 0x58, 4, "C5_RES (Mobile)" },
 	{ 0x5c, 4, "RESERVED" },
 	/* Here start the TCO registers */
 	{ 0x60, 2, "TCO_RLD" },
@@ -145,6 +145,67 @@ static const io_register_t ich8_pm_registers[] = {
 	{ 0x7c, 4, "RESERVED" },
 };
 
+static const io_register_t ich7_pm_registers[] = {
+	{ 0x00, 2, "PM1_STS" },
+	{ 0x02, 2, "PM1_EN" },
+	{ 0x04, 4, "PM1_CNT" },
+	{ 0x08, 4, "PM1_TMR" },
+	{ 0x0c, 4, "RESERVED" },
+	{ 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+	/* These registers return 0 on read, but reading them may cause
+	 * the system to enter C2/C3/C4 state, which might hang the system.
+	 */
+	{ 0x14, 1, "LV2 (Mobile/Ultra Mobile)" },
+	{ 0x15, 1, "LV3 (Mobile/Ultra Mobile)" },
+	{ 0x16, 1, "LV4 (Mobile/Ultra Mobile)" },
+#endif
+	{ 0x17, 1, "RESERVED" },
+	{ 0x18, 4, "RESERVED" },
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" },
+	{ 0x21, 1, "RESERVED" },
+	{ 0x22, 2, "RESERVED" },
+	{ 0x24, 4, "RESERVED" },
+	{ 0x28, 4, "GPE0_STS" },
+	{ 0x2C, 4, "GPE0_EN" },
+	{ 0x30, 4, "SMI_EN" },
+	{ 0x34, 4, "SMI_STS" },
+	{ 0x38, 2, "ALT_GP_SMI_EN" },
+	{ 0x3a, 2, "ALT_GP_SMI_STS" },
+	{ 0x3c, 4, "RESERVED" },
+	{ 0x40, 2, "RESERVED" },
+	{ 0x42, 1, "GPE_CNTL" },
+	{ 0x43, 1, "RESERVED" },
+	{ 0x44, 2, "DEVACT_STS" },
+	{ 0x46, 2, "RESERVED" },
+	{ 0x48, 4, "RESERVED" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
+	{ 0x51, 1, "RESERVED" },
+	{ 0x52, 2, "RESERVED" },
+	{ 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" },
+	{ 0x58, 4, "RESERVED" },
+	{ 0x5c, 4, "RESERVED" },
+	/* Here start the TCO registers */
+	{ 0x60, 2, "TCO_RLD" },
+	{ 0x62, 1, "TCO_DAT_IN" },
+	{ 0x63, 1, "TCO_DAT_OUT" },
+	{ 0x64, 2, "TCO1_STS" },
+	{ 0x66, 2, "TCO2_STS" },
+	{ 0x68, 2, "TCO1_CNT" },
+	{ 0x6a, 2, "TCO2_CNT" },
+	{ 0x6c, 2, "TCO_MESSAGE" },
+	{ 0x6e, 1, "TCO_WDCNT" },
+	{ 0x6f, 1, "RESERVED" },
+	{ 0x70, 1, "SW_IRQ_GEN" },
+	{ 0x71, 1, "RESERVED" },
+	{ 0x72, 2, "TCO_TMR" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
 /*
  * INTEL I/O Controller Hub 6 Family
  * http://www.intel.com/assets/pdf/datasheet/301473.pdf
@@ -357,6 +418,16 @@ int print_pmbase(struct pci_dev *sb)
 		pm_registers = ich7_pm_registers;
 		size = ARRAY_SIZE(ich7_pm_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_ICH9DH:
+	case PCI_DEVICE_ID_INTEL_ICH9DO:
+	case PCI_DEVICE_ID_INTEL_ICH9R:
+	case PCI_DEVICE_ID_INTEL_ICH9:
+	case PCI_DEVICE_ID_INTEL_ICH9M:
+	case PCI_DEVICE_ID_INTEL_ICH9ME:
+		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+		pm_registers = ich9_pm_registers;
+		size = ARRAY_SIZE(ich9_pm_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH8M:
 		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
 		pm_registers = ich8_pm_registers;