diff options
| author | Christoph Pomaska <cp_public@gmx.de> | 2018-01-01 01:48:21 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-01-10 22:04:33 +0000 |
| commit | 48ac29ee4cbd159932d919a3d791cfe42d950b28 (patch) | |
| tree | 304b8699a746ab60a38db9f7ef48cd339d4c39ef /util/inteltool/pcie.c | |
| parent | bb9bdeb59480cade6f428237c6727d805d6c5f4c (diff) | |
util/inteltool: Add Skylake Desktop Northbridge
Add the 8086:191f North/Host Bridge to the list of definitions.
Adding the definiton makes the Northbridge get recognized by inteltool.
It is found in the Intel i5-6600K CPU:
https://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz
Change-Id: Id746d1e8b3bb90b3b68a2f6c372890671dd61b5f
Signed-off-by: Christoph Pomaska <cp_public@gmx.de>
Reviewed-on: https://review.coreboot.org/23055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util/inteltool/pcie.c')
| -rw-r--r-- | util/inteltool/pcie.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 78d69feda3..2eb65c1819 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -265,6 +265,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -385,6 +386,7 @@ int print_dmibar(struct pci_dev *nb) break; case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: dmi_registers = skylake_dmi_registers; size = ARRAY_SIZE(skylake_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -489,6 +491,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; |