diff options
| author | Brandon Weeks <me@brandonweeks.com> | 2023-12-26 15:55:03 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-03-13 13:59:31 +0000 |
| commit | 7ee7b137a7638f5e9d85bd88e52e6391da0ebcbb (patch) | |
| tree | 9a517174ad447372a1fbd9d85f5cae9bbae0ee49 /util/inteltool/pcie.c | |
| parent | 30bd24fd267af34b9e12408cd6a2cda27c893ebd (diff) | |
util/inteltool: Add support for Alder Lake-N
Reference: Intel Processor and Intel Core i3 N-Series Datasheet,
Volume 1 of 2 (#759603)
Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562
Signed-off-by: Brandon Weeks <me@brandonweeks.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'util/inteltool/pcie.c')
| -rw-r--r-- | util/inteltool/pcie.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index fb29d3201e..7303811b67 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -202,6 +202,30 @@ static const io_register_t skylake_dmi_registers[] = { { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask }; +static const io_register_t alderlake_dmi_registers[] = { + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ + { 0x44, 4, "DMIESD" }, // DMI Element Self Description + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address + { 0x88, 2, "LCTL" }, // Link Control + { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status + { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask + { 0x1CC, 4, "DMIUESEV" }, // DMI Uncorrectable Error Mask + { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status + { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask +}; /* * Egress Port Root Complex MMIO configuration space @@ -265,6 +289,9 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -404,6 +431,14 @@ int print_dmibar(struct pci_dev *nb) dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmi_registers = alderlake_dmi_registers; + size = ARRAY_SIZE(alderlake_dmi_registers); + break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; @@ -515,6 +550,9 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; |