inteltool: new definitions and cleanup

 - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
 - Refine some names and macros.
 - Clean up some whitespace errors.

 - Add IDs and names of 5, 6 and 7 Series southbridges and the three
   latest Core CPU families with integrated memory controllers but do
   not implement any pretty printing routines for them yet.

   The first generation Core family is already supported, although it
   was wrongly named after the PCH and used the wrong ID. Also, the BAR
   values have been mangled to 32b instead of 64b. Both errors have been
   fixed and most basic support for the other two generations was added.

Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1574
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

1 files changed, 36 insertions, 26 deletions

diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index d66ee4884d..62d72177b0 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -108,20 +108,20 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 	case PCI_DEVICE_ID_INTEL_82945GM:
 	case PCI_DEVICE_ID_INTEL_82945GSE:
 	case PCI_DEVICE_ID_INTEL_82945P:
- 	case PCI_DEVICE_ID_INTEL_82975X:
+	case PCI_DEVICE_ID_INTEL_82975X:
 		mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
 		break;
- 	case PCI_DEVICE_ID_INTEL_PM965:
- 	case PCI_DEVICE_ID_INTEL_82Q35:
- 	case PCI_DEVICE_ID_INTEL_82G33:
- 	case PCI_DEVICE_ID_INTEL_82Q33:
- 		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
- 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
- 		break;
- 	case PCI_DEVICE_ID_INTEL_Q965:
+	case PCI_DEVICE_ID_INTEL_82965PM:
+	case PCI_DEVICE_ID_INTEL_82Q35:
+	case PCI_DEVICE_ID_INTEL_82G33:
+	case PCI_DEVICE_ID_INTEL_82Q33:
+		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
+		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+		break;
+	case PCI_DEVICE_ID_INTEL_82Q965:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
- 		mchbar_phys = pci_read_long(nb, 0x48);
+		mchbar_phys = pci_read_long(nb, 0x48);
 
 		/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
 		 * If it isn't, try to set it. This may fail, because there is
@@ -131,36 +131,45 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 
 		if(!(mchbar_phys & 1))
 		{
-			printf("Access to the MCHBAR is currently disabled, "\
-						"attempting to enable.\n");
+			printf("Access to the MCHBAR is currently disabled, "
+				   "attempting to enable.\n");
 			mchbar_phys |= 0x1;
 			pci_write_long(nb, 0x48, mchbar_phys);
-	 		if(pci_read_long(nb, 0x48) & 1)
+			if(pci_read_long(nb, 0x48) & 1)
 				printf("Enabled successfully.\n");
 			else
 				printf("Enable FAILED!\n");
 		}
 		mchbar_phys &= 0xfffffffe;
- 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
- 		break;
+		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+		break;
 	case PCI_DEVICE_ID_INTEL_82443LX:
 	case PCI_DEVICE_ID_INTEL_82443BX:
 	case PCI_DEVICE_ID_INTEL_82810:
-	case PCI_DEVICE_ID_INTEL_82810E_MC:
-	case PCI_DEVICE_ID_INTEL_82810DC:
+	case PCI_DEVICE_ID_INTEL_82810E_DC:
+	case PCI_DEVICE_ID_INTEL_82810_DC:
 	case PCI_DEVICE_ID_INTEL_82830M:
 		printf("This northbridge does not have MCHBAR.\n");
 		return 1;
-	case PCI_DEVICE_ID_INTEL_GS45:
-	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_82X4X:
+	case PCI_DEVICE_ID_INTEL_82X38:
 	case PCI_DEVICE_ID_INTEL_32X0:
 		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
- 		break;
-	case PCI_DEVICE_ID_INTEL_HM65E:
-		mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000;
+		break;
+	case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
+		mchbar_phys = pci_read_long(nb, 0x48);
+		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+		mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
+		mch_registers = NULL; /* No public documentation */
+		break;
+	case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
 		mch_registers = sandybridge_mch_registers;
 		size = ARRAY_SIZE(sandybridge_mch_registers);
+	case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
+		mchbar_phys = pci_read_long(nb, 0x48);
+		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+		mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
 		break;
 	default:
 		printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
@@ -183,28 +192,29 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 		printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
 
 	if (mch_registers != NULL) {
+		printf("%d registers:\n", size);
 		for (i = 0; i < size; i++) {
 			switch (mch_registers[i].size) {
 				case 8:
-					printf("mchbase+0x%04x: 0x%08lx (%s)\n",
+					printf("mchbase+0x%04x: 0x%016lx (%s)\n",
 						mch_registers[i].addr,
 						*(uint64_t *)(mchbar+mch_registers[i].addr),
 						mch_registers[i].name);
 					break;
 				case 4:
-					printf("mchbase+0x%04x: 0x%08x (%s)\n",
+					printf("mchbase+0x%04x: 0x%08x         (%s)\n",
 						mch_registers[i].addr,
 						*(uint32_t *)(mchbar+mch_registers[i].addr),
 						mch_registers[i].name);
 					break;
 				case 2:
-					printf("mchbase+0x%04x: 0x%04x     (%s)\n",
+					printf("mchbase+0x%04x: 0x%04x             (%s)\n",
 						mch_registers[i].addr,
 						*(uint16_t *)(mchbar+mch_registers[i].addr),
 						mch_registers[i].name);
 					break;
 				case 1:
-					printf("mchbase+0x%04x: 0x%02x       (%s)\n",
+					printf("mchbase+0x%04x: 0x%02x               (%s)\n",
 						mch_registers[i].addr,
 						*(uint8_t *)(mchbar+mch_registers[i].addr),
 						mch_registers[i].name);