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authorBrandon Weeks <me@brandonweeks.com>2023-12-26 15:55:03 -0800
committerFelix Held <felix-coreboot@felixheld.de>2024-03-13 13:59:31 +0000
commit7ee7b137a7638f5e9d85bd88e52e6391da0ebcbb (patch)
tree9a517174ad447372a1fbd9d85f5cae9bbae0ee49 /util/inteltool/memory.c
parent30bd24fd267af34b9e12408cd6a2cda27c893ebd (diff)
util/inteltool: Add support for Alder Lake-N
Reference: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2 (#759603) Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562 Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'util/inteltool/memory.c')
-rw-r--r--util/inteltool/memory.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 6df878255d..2ae331a576 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -148,6 +148,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_82Q965:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
+ case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
+ case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
+ case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
mchbar_phys = pci_read_long(nb, 0x48);
/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.