diff options
| author | Brandon Weeks <me@brandonweeks.com> | 2023-12-26 15:55:03 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-03-13 13:59:31 +0000 |
| commit | 7ee7b137a7638f5e9d85bd88e52e6391da0ebcbb (patch) | |
| tree | 9a517174ad447372a1fbd9d85f5cae9bbae0ee49 /util/inteltool/lpc.c | |
| parent | 30bd24fd267af34b9e12408cd6a2cda27c893ebd (diff) | |
util/inteltool: Add support for Alder Lake-N
Reference: Intel Processor and Intel Core i3 N-Series Datasheet,
Volume 1 of 2 (#759603)
Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562
Signed-off-by: Brandon Weeks <me@brandonweeks.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'util/inteltool/lpc.c')
| -rw-r--r-- | util/inteltool/lpc.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c index 2d3c91c704..8e171e3afb 100644 --- a/util/inteltool/lpc.c +++ b/util/inteltool/lpc.c @@ -57,6 +57,26 @@ static const io_register_t sunrise_espi_cfg_registers[] = { {0xDC, 4, "ESPI_BC"}, }; +static const io_register_t alderlake_espi_cfg_registers[] = { + {0x00, 4, "ESPI_DID_VID"}, + {0x04, 4, "ESPI_STS_CMD"}, + {0x08, 4, "ESPI_CC_RID"}, + {0x2C, 4, "ESPI_SS"}, + {0x34, 4, "ESPI_CAPP"}, + {0x80, 4, "ESPI_IOD_IOE"}, + {0x84, 4, "ESPI_LGIR1"}, + {0x88, 4, "ESPI_LGIR2"}, + {0x8C, 4, "ESPI_LGIR3"}, + {0x90, 4, "ESPI_LGIR4"}, + {0x94, 4, "ESPI_ULKMC"}, + {0x98, 4, "ESPI_LGMR"}, + {0xA0, 4, "ESPI_CS1IORE"}, + {0xA4, 4, "ESPI_CS1GIR1"}, + {0xA8, 4, "ESPI_CS1GMR1"}, + {0xD8, 4, "ESPI_BDE"}, + {0xDC, 4, "ESPI_BC"}, +}; + int print_lpc(struct pci_dev *sb, struct pci_access *pacc) { size_t i, cfg_registers_size = 0; @@ -108,7 +128,16 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc) cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers); } break; - + case PCI_DEVICE_ID_INTEL_ADL_N: + dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); + if (!dev) { + printf("LPC/eSPI interface not found.\n"); + return 1; + } + printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n"); + cfg_registers = alderlake_espi_cfg_registers; + cfg_registers_size = ARRAY_SIZE(alderlake_espi_cfg_registers); + break; default: printf("Error: Dumping LPC/eSPI on this southbridge is not (yet) supported.\n"); return 1; |