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authorNico Huber <nico.huber@secunet.com>2017-04-05 17:39:57 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2018-01-15 01:18:05 +0000
commit99b02a1d7c486d0b4083cbfdafe2a92de4975362 (patch)
treed4221e5772446d5158f642bec6cfbc20fe351aa6 /util/inteltool/inteltool.h
parent76a4f71e89722fd579daa559a1d24b3d710dbed6 (diff)
inteltool: Support for nasty Primary to Sideband Bridge (P2SB)
The Primary to Sideband Bridge (P2SB) is the interface to Private Con- figuration Registers (PCR) including GPIO configuration. Of course, access is restricted to Intel partners and criminals, so the PCI device is hidden from the OS. Probably we only need to fetch the SBREG_BAR address and can hide the PCI device again after that. Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'util/inteltool/inteltool.h')
-rw-r--r--util/inteltool/inteltool.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 512bdbaee3..22eda6ead8 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -14,6 +14,9 @@
* GNU General Public License for more details.
*/
+#ifndef INTELTOOL_H
+#define INTELTOOL_H 1
+
#include <commonlib/helpers.h>
#include <stdint.h>
@@ -139,6 +142,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141
#define PCI_DEVICE_ID_INTEL_H110 0xa143
#define PCI_DEVICE_ID_INTEL_H170 0xa144
@@ -307,3 +311,5 @@ int print_gfx(struct pci_dev *gfx);
int print_ahci(struct pci_dev *ahci);
int print_sgx(void);
void ivybridge_dump_timings(const char *dump_spd_file);
+
+#endif