diff options
| author | Alexander Couzens <lynxis@fe80.eu> | 2023-11-30 18:13:35 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-10-02 12:38:05 +0000 |
| commit | 744e93e8b0f7214f4b9867a896dfa40087608faf (patch) | |
| tree | 411b05c2444821cd3465b26b43cff67100310199 /util/inteltool/inteltool.h | |
| parent | 4e92938fd1219513284d861edc9742854c790c64 (diff) | |
inteltool: improve support for Elkhart Lake
Add support for SPI/flash, LPC/eSPI, MCH and
add pci vendor/product description.
References:
* CPU: Linux kernel
* GPU: Linux kernel
* GPU: https://dgpu-docs.intel.com/devices/hardware-table.html
* Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series
Processors for IoT Applications, February 2023, 636722
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75214
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/inteltool/inteltool.h')
| -rw-r--r-- | util/inteltool/inteltool.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 9ed958c736..f44c79c5fc 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -344,6 +344,19 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc #define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31E8 +/* Elkhart Lake */ +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_1 0x4514 +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_2 0x4516 +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_3 0x4518 +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_4 0x451a +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_5 0x4528 +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_6 0x452a +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_7 0x452c +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_8 0x452e +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_9 0x4532 +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_10 0x4534 +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_11 0x4536 + /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D 0x0040 /* Clarkdale (Westmere Desktop) */ @@ -486,6 +499,13 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70 +/* Elkhart Lake */ +#define PCI_DEVICE_ID_INTEL_EHL_GT1_1 0x4541 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_2 0x4551 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4555 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_4 0x4557 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_5 0x4570 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_6 0x4571 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_2 0x4682 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_3 0x4690 @@ -538,7 +558,7 @@ int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); int print_ambs(struct pci_dev *nb, struct pci_access *pacc); -int print_spi(struct pci_dev *sb); +int print_spi(struct pci_dev *sb, struct pci_access *pacc); int print_gfx(struct pci_dev *gfx); int print_ahci(struct pci_dev *ahci); int print_sgx(void); |