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| author | Stefan Tauner <stefan.tauner@gmx.at> | 2013-06-20 18:05:06 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-23 23:36:03 +0200 |
| commit | dbc6fcd021759280c71b0e246c0ede34f4879bac (patch) | |
| tree | cec3448dd91f0ea075ce5f7d58b1809dc00925c8 /util/inteltool/inteltool.h | |
| parent | a390d779668146b60fdb89eaa709054d7811df7e (diff) | |
inteltool: add initial support for Nehalem
Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)
Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.
The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...
Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'util/inteltool/inteltool.h')
| -rw-r--r-- | util/inteltool/inteltool.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index dc5c832e6e..88008e4e17 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -151,6 +151,7 @@ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 /* Intel starts counting these generations with the integration of the DRAM controller */ +#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */ #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */ |