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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2022-07-27 04:11:26 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-10 14:42:37 +0000 |
| commit | 12367e0db1150cfb6c75af3e5a41a0e409f7a0c1 (patch) | |
| tree | a3437be3d74e829bfaa471fa7baed54b7a9fd534 /util/inteltool/inteltool.c | |
| parent | 21c3c44ef55d5ed3b69ea34fb2c8ee7541fde253 (diff) | |
mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'util/inteltool/inteltool.c')
0 files changed, 0 insertions, 0 deletions