diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-16 12:49:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-09 22:00:00 +0000 |
| commit | 472d83bb0af27875f41232ec75e04b082108b0e1 (patch) | |
| tree | b110297fb7f05adcdf77a6bd09abd2920adc9cff /util/inteltool/gpio_names | |
| parent | 8c1154dc6168e8df62c2d5da054508e3e7b28dbe (diff) | |
intetool: Add support for 700 series PCH
The change does the following:
- adds PCH IDs for 700 series chipsets per the DOC# 619362 rev 2.2
- updates GPIO table for PCH-S per the DOC# 618659 rev 2.1
- enables dumping GPIOs for 700 series PCH
Change-Id: I4509ad714772ce90cdee5135227c02640acb6085
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'util/inteltool/gpio_names')
| -rw-r--r-- | util/inteltool/gpio_names/alderlake_h.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/util/inteltool/gpio_names/alderlake_h.h b/util/inteltool/gpio_names/alderlake_h.h index 0a563f0440..d3a9ed6137 100644 --- a/util/inteltool/gpio_names/alderlake_h.h +++ b/util/inteltool/gpio_names/alderlake_h.h @@ -105,10 +105,10 @@ const char *const alderlake_pch_h_group_d_names[] = { "GPP_D2", "SRCCLKREQ2#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D2", "GPP_D3", "SRCCLKREQ3#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D3", "GPP_D4", "SML1CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D4", - "GPP_D5", "n/a", "CNV_RF_RESET#", "n/a", "n/a", "n/a", "USB_C_GPP_D5", - "GPP_D6", "n/a", "n/a", "MODEM_CLKREQ", "n/a", "n/a", "USB_C_GPP_D6", - "GPP_D7", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D7", - "GPP_D8", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D8", + "GPP_D5", "I2S2_SFRM", "CNV_RF_RESET#", "n/a", "n/a", "n/a", "USB_C_GPP_D5", + "GPP_D6", "I2S2_TXD", "n/a", "MODEM_CLKREQ", "n/a", "n/a", "USB_C_GPP_D6", + "GPP_D7", "I2S2_RXD", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D7", + "GPP_D8", "I2S2_SCLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D8", "GPP_D9", "SML0CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D9", "GPP_D10", "SML0DATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D10", "GPP_D11", "SRCCLKREQ4#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D11", @@ -339,15 +339,15 @@ const struct gpio_group alderlake_pch_h_group_k = { }; const char *const alderlake_pch_h_group_r_names[] = { - "GPP_R0", "HDA_BCLK", "n/a", "n/a", "HDACPU_BCLK", "n/a", "USB_C_GPP_R0", - "GPP_R1", "HDA_SYNC", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R1", - "GPP_R2", "HDA_SDO", "n/a", "n/a", "HDACPU_SDO", "n/a", "USB_C_GPP_R2", - "GPP_R3", "HDA_SDI0", "n/a", "n/a", "HDACPU_SDI", "n/a", "USB_C_GPP_R3", + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", "n/a", "HDACPU_BCLK", "n/a", "USB_C_GPP_R0", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", "n/a", "n/a", "n/a", "USB_C_GPP_R1", + "GPP_R2", "HDA_SDO", "I2S0_TXD", "n/a", "HDACPU_SDO", "n/a", "USB_C_GPP_R2", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", "n/a", "HDACPU_SDI", "n/a", "USB_C_GPP_R3", "GPP_R4", "HDA_RST#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R4", - "GPP_R5", "HDA_SDI1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R5", - "GPP_R6", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R6", - "GPP_R7", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R7", - "GPP_R8", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_R8", + "GPP_R5", "HDA_SDI1", "I2S1_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_R5", + "GPP_R6", "n/a", "I2S1_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_R6", + "GPP_R7", "n/a", "I2S1_SFRM", "n/a", "n/a", "n/a", "USB_C_GPP_R7", + "GPP_R8", "n/a", "I2S1_SCLK", "n/a", "n/a", "n/a", "USB_C_GPP_R8", "GPP_R9", "DDSP_HPDA", "DISP_MISCA", "n/a", "n/a", "n/a", "USB_C_GPP_R9", "GPP_R10", "DDSP_HPDB", "DISP_MISCB", "n/a", "n/a", "n/a", "USB_C_GPP_R10", "GPP_R11", "DDSP_HPDC", "DISP_MISCC", "n/a", "n/a", "n/a", "USB_C_GPP_R11", |