This patch adds:

 ICH6 Southbridge,
 82915 Series Northbridge,
 P4 6xx Series CPU

to inteltool

Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630 
installed.

Signed-off-by: Pat Erley <pat-lkml@erley.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 138 insertions, 0 deletions

diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index e6b28c087a..dd23d8196f 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -307,6 +307,143 @@ int print_intel_core_msrs(void)
 		//{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
 	};
 
+	/* Pentium 4 and XEON */
+	/* 
+	 * All MSRs per 
+	 *
+	 * Intel® 64 and IA-32 Architectures
+	 * Software Developer.s Manual
+	 * Volume 3B:
+	 * System Programming Guide, Part 2
+	 *
+	 * Table B-5
+	 */
+	static const msr_entry_t modelf4x_global_msrs[] = {
+		{ 0x0000, "IA32_P5_MC_ADDR" },
+		{ 0x0001, "IA32_P5_MC_TYPE" },
+		{ 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
+		{ 0x0017, "IA32_PLATFORM_ID" },
+		{ 0x002a, "MSR_EBC_HARD_POWERON" },
+		{ 0x002b, "MSR_EBC_SOFT_POWRON" },
+		{ 0x002c, "MSR_EBC_FREQUENCY_ID" },
+// WRITE ONLY	{ 0x0079, "IA32_BIOS_UPDT_TRIG" },		
+		{ 0x019c, "IA32_THERM_STATUS" },
+		{ 0x019d, "MSR_THERM2_CTL" },
+		{ 0x01a0, "IA32_MISC_ENABLE" },
+		{ 0x01a1, "MSR_PLATFORM_BRV" },
+		{ 0x0200, "IA32_MTRR_PHYSBASE0" },
+		{ 0x0201, "IA32_MTRR_PHYSMASK0" },
+		{ 0x0202, "IA32_MTRR_PHYSBASE1" },
+		{ 0x0203, "IA32_MTRR_PHYSMASK1" },
+		{ 0x0204, "IA32_MTRR_PHYSBASE2" },
+		{ 0x0205, "IA32_MTRR_PHYSMASK2" },
+		{ 0x0206, "IA32_MTRR_PHYSBASE3" },
+		{ 0x0207, "IA32_MTRR_PHYSMASK3" },
+		{ 0x0208, "IA32_MTRR_PHYSBASE4" },
+		{ 0x0209, "IA32_MTRR_PHYSMASK4" },
+		{ 0x020a, "IA32_MTRR_PHYSBASE5" },
+		{ 0x020b, "IA32_MTRR_PHYSMASK5" },
+		{ 0x020c, "IA32_MTRR_PHYSBASE6" },
+		{ 0x020d, "IA32_MTRR_PHYSMASK6" },
+		{ 0x020e, "IA32_MTRR_PHYSBASE7" },
+		{ 0x020f, "IA32_MTRR_PHYSMASK7" },
+		{ 0x0250, "IA32_MTRR_FIX64K_00000" },
+		{ 0x0258, "IA32_MTRR_FIX16K_80000" },
+		{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
+		{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
+		{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
+		{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
+		{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
+		{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
+		{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
+		{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
+		{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
+		{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
+		{ 0x0300, "MSR_BPU_COUNTER0" },
+		{ 0x0301, "MSR_BPU_COUNTER1" },
+		{ 0x0302, "MSR_BPU_COUNTER2" },
+		{ 0x0303, "MSR_BPU_COUNTER3" },
+		/* Skipped through 0x3ff  for now*/
+
+	/* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being 
+	 * set in MCX_STATUS */
+		{ 0x400, "IA32_MC0_CTL" },
+		{ 0x401, "IA32_MC0_STATUS" },
+		{ 0x402, "IA32_MC0_ADDR" },
+		{ 0x403, "IA32_MC0_MISC" },
+		{ 0x404, "IA32_MC1_CTL" },
+		{ 0x405, "IA32_MC1_STATUS" },
+		{ 0x406, "IA32_MC1_ADDR" },
+		{ 0x407, "IA32_MC1_MISC" }, 
+		{ 0x408, "IA32_MC2_CTL" },
+		{ 0x409, "IA32_MC2_STATUS" },
+		{ 0x40a, "IA32_MC2_ADDR" },
+		{ 0x40b, "IA32_MC2_MISC" },
+		{ 0x40c, "IA32_MC3_CTL" },
+		{ 0x40d, "IA32_MC3_STATUS" },
+		{ 0x40e, "IA32_MC3_ADDR" },
+		{ 0x40f, "IA32_MC3_MISC" },
+		{ 0x410, "IA32_MC4_CTL" },
+		{ 0x411, "IA32_MC4_STATUS" },
+		{ 0x412, "IA32_MC4_ADDR" },
+		{ 0x413, "IA32_MC4_MISC" },
+	};
+
+	static const msr_entry_t modelf4x_per_core_msrs[] = {
+		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
+		{ 0x001b, "IA32_APIC_BASE" },
+		{ 0x003a, "IA32_FEATURE_CONTROL" },
+		{ 0x008b, "IA32_BIOS_SIGN_ID" },
+		{ 0x009b, "IA32_SMM_MONITOR_CTL" },
+		{ 0x00fe, "IA32_MTRRCAP" },
+		{ 0x0174, "IA32_SYSENTER_CS" },
+		{ 0x0175, "IA32_SYSENTER_ESP" },
+		{ 0x0176, "IA32_SYSENTER_EIP" },
+		{ 0x0179, "IA32_MCG_CAP" },
+		{ 0x017a, "IA32_MCG_STATUS" },
+		{ 0x0180, "MSR_MCG_RAX" },
+		{ 0x0181, "MSR_MCG_RBX" },
+		{ 0x0182, "MSR_MCG_RCX" },
+		{ 0x0183, "MSR_MCG_RDX" },
+		{ 0x0184, "MSR_MCG_RSI" },
+		{ 0x0185, "MSR_MCG_RDI" },
+		{ 0x0186, "MSR_MCG_RBP" },
+		{ 0x0187, "MSR_MCG_RSP" },
+		{ 0x0188, "MSR_MCG_RFLAGS" },
+		{ 0x0189, "MSR_MCG_RIP" },
+		{ 0x018a, "MSR_MCG_MISC" },
+		// 0x18b-f Reserved
+		{ 0x0190, "MSR_MCG_R8" },
+		{ 0x0191, "MSR_MCG_R9" },
+		{ 0x0192, "MSR_MCG_R10" },
+		{ 0x0193, "MSR_MCG_R11" },
+		{ 0x0194, "MSR_MCG_R12" },
+		{ 0x0195, "MSR_MCG_R13" },
+		{ 0x0196, "MSR_MCG_R14" },
+		{ 0x0197, "MSR_MCG_R15" },
+		{ 0x0198, "IA32_PERF_STATUS" },
+		{ 0x0199, "IA32_PERF_CTL" },
+		{ 0x019a, "IA32_CLOCK_MODULATION" },
+		{ 0x019b, "IA32_THERM_INTERRUPT" },
+		{ 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
+		{ 0x01d7, "MSR_LER_FROM_LIP" },
+		{ 0x01d8, "MSR_LER_TO_LIP" },
+		{ 0x01d9, "MSR_DEBUGCTLA" },
+		{ 0x01da, "MSR_LASTBRANCH_TOS" },
+		{ 0x0277, "IA32_PAT" },
+		/** Virtualization
+		{ 0x480, "IA32_VMX_BASIC" },
+		  through
+		{ 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
+		  Not implemented in my CPU
+		*/
+		{ 0x0600, "IA32_DS_AREA" },
+		/* 0x0680 - 0x06cf Branch Records Skipped */
+	
+	};
+
+
+
 	typedef struct {
 		unsigned int model;
 		const msr_entry_t *global_msrs;
@@ -319,6 +456,7 @@ int print_intel_core_msrs(void)
 		{ 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
 		{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
 		{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
+		{ 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
 	};
 
 	cpu_t *cpu = NULL;