diff options
| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-11-06 17:19:44 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 11:08:27 +0000 |
| commit | 1bb640dfc0affdb48206661504825586593c8ec2 (patch) | |
| tree | 39f237cb9e080c220e586048090ed037bfc20cec /util/intelp2m/platforms/snr | |
| parent | f41645c34d8b22a3d887abd56138ae794fc2dfa5 (diff) | |
util/intelp2m: Clean up SCI, SMI macro generation and update comments
Simplify macro generation and fix up "DEEP,EDGE_SINGLE" bug introduced
by commit 7bb756f (util/intelp2m: Update macros). Also update legacy
macro comments.
Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47314
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/intelp2m/platforms/snr')
| -rw-r--r-- | util/intelp2m/platforms/snr/macro.go | 30 |
1 files changed, 6 insertions, 24 deletions
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 43d373ee84..fb530c54c1 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -90,12 +90,12 @@ func ioApicRoute() bool { macro.Add("_APIC") if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL { if dw0.GetRxInvert() != 0 { - // PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) + // PAD_CFG_GPI_APIC_LOW(pad, pull, rst) macro.Add("_LOW") } else { + // PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) macro.Add("_HIGH") } - // PAD_CFG_GPI_APIC(pad, pull, rst) macro.Add("(").Id().Pull().Rstsrc().Add("),") return true } @@ -123,18 +123,8 @@ func sciRoute() bool { if dw0.GetGPIOInputRouteSCI() == 0 { return false } - macro.Add("_SCI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - macro.Trig() - } - // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { - // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), - // #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ - // PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) - macro.Add(",").Add("EDGE_SINGLE") - } - macro.Invert().Add("),") + // PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") return true } @@ -145,16 +135,8 @@ func smiRoute() bool { if dw0.GetGPIOInputRouteSMI() == 0 { return false } - macro.Add("_SMI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { - // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), - macro.Add(",").Add("EDGE_SINGLE") - } - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - // e.g. PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), - macro.Trig() - } - macro.Invert().Add("),") + // PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") return true } |