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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-06-13 11:00:56 +0530
committerMartin Roth <martinroth@google.com>2017-07-28 16:17:26 +0000
commita1af090002193ef5f202b605397af067ce15caa2 (patch)
tree30ddc4bc440a797abc6c7b100bfbbb6db470d79b /util/intelmetool
parentff1477911e2b33f0d2dcbf1405b628f48e994c8a (diff)
soc/intel/skylake: Remove incorrect ME PG-status print
As per discussion with CSME team, ME is NOT using PCI Config Space register HFSTS2 Bit 10 to update ME power-gated status. ME goes to CM0-PG state after ME device becomes idle after Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C) is being set. And to retrieve the PG status of ME, one should read from the PWRMBASE+offset 0x590 (which should give the value 0xF9) and PWRMBASE+offset 0x594 (which should give the value 0xFF). But, also it needs some time for the ME FW to go to idle state and reflect these values in PWRMBASE registers after D0i3 bit is being set. This does not happen instantly. So, in coreboot, if we read the ME PG state in finalize.c, which happens just after FSP Notify phase, where actually ME D0i3 bit is set, we do not read the correct PG state values (i.e, 0xF9 and 0xFF). But, once it boots to Kernel, if we read those same registers through iotool mmio_read32 command, we get correct values. So, removing the ME PG state prints from coreboot, since it is actually showing wrong information, although ME Power Gating is successful. Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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