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authorAaron Durbin <adurbin@chromium.org>2017-06-08 10:52:58 -0500
committerAaron Durbin <adurbin@chromium.org>2017-06-09 18:28:23 +0200
commit0b34fc6f54074673099e267a0806c656afd68172 (patch)
treec11409d66f76b23a5b1f1033869257022b46c13b /util/intelmetool
parentea0497c786aa8103adc2b178cc4fe714cb008281 (diff)
soc/intel/common/fast_spi: support caching bios in ramstage
After the MTRR solution has been calculated provide a way for code to call the same function, fast_spi_cache_bios_region(), in all stages. This is accomplished by using the ramstage temporary MTRR support. Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20115 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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