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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2016-09-27 23:18:35 +0530
committerAaron Durbin <adurbin@chromium.org>2016-10-16 02:51:52 +0200
commita247d8e53cebbd754e46f76412ed9d17df752308 (patch)
tree32c3fcf219f97debcdfecfa0f77117e0d0549bfa /util/intelmetool/mmap.h
parent9a20551b7e15ff8bb05922489ee4649f1b7f4826 (diff)
soc/intel/apollolake: Set PL1 limits for RAPL MSR registers
This patch sets the package power limit (PL1) value in RAPL MSR and disables MMIO register. Added configurable PL1 override parameter to leverage full TDP capacity. BUG=chrome-os-partner:56922 TEST=webGL performance(fps) not impacted before and after S3. Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16884 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/intelmetool/mmap.h')
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