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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-07-28 11:34:41 -0600
committerPaul Fagerburg <pfagerburg@chromium.org>2021-09-20 15:44:16 +0000
commit56791b2841ab8e2e42ced01ee143572cfc360b8e (patch)
treeb7870c33bb5485184b21c8eea45e74e652ab8fe2 /util/intelmetool/me_status.c
parent38d38479faa426f0fed8c84336b55713041efea9 (diff)
soc/intel/elkhartlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'util/intelmetool/me_status.c')
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