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authorSridahr Siricilla <sridhar.siricilla@intel.com>2021-06-18 10:59:30 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-21 18:54:39 +0000
commit54b03569c3aaa7f03e0569223e0fb6d42bbdda56 (patch)
tree6467c4d0fcf55ee892c81bb6092e52970cebc9ec /util/intelmetool/me.c
parent42583de6b8e2692962e2ec86136fe7ae2b42e162 (diff)
soc/intel/common: Check CSE Lite RW status
The patch moves CSE Lite RW status check out of CSE RW update logic as the RW sanity check has to be done irrespective of CSE RW update logic is enabled or not. If coreboot detects CSE Lite RW status is not good, the coreboot triggers recovery. TEST=Verified boot on Brya Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com> Change-Id: I582b6cf24f8894c80ab461ca21f7c6e8caa738bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55619 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/intelmetool/me.c')
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