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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-07-28 11:33:28 -0600
committerPaul Fagerburg <pfagerburg@chromium.org>2021-09-20 15:44:12 +0000
commit38d38479faa426f0fed8c84336b55713041efea9 (patch)
treeebe39f4539725c840c9202acc208608390a04155 /util/intelmetool/Makefile
parentff8d0e64a7b3b60f646014523054eb96ec919112 (diff)
soc/intel/icelake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I1a55df754c711b2afb8939b442019831c25cce29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'util/intelmetool/Makefile')
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