soc/intel/cannonlake: Add options for pcie ltr

FSP can support enable/disable Pci express LTR (Latency Tolerance
Reporting) mechanism through upd interface. Include that into coreboot
side.

BUG=N/A
TEST=N/A

Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29642
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions