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authorWerner Zeh <werner.zeh@siemens.com>2016-07-06 11:59:10 +0200
committerWerner Zeh <werner.zeh@siemens.com>2016-07-07 06:20:16 +0200
commite1d6aa6e4195f5fce6cb65d39d36289e6786fa36 (patch)
tree2f1e7fe5036d828b62452606c90bb2e3dc96488d /util/ifdfake/Makefile
parent93db5a5eeea78423ca763bff013d3610655e3776 (diff)
siemens/mc_bdx1: Set up opcode menu for SPI controller
Since SPI controller opcode registers are locked by FSP, they need to be initialized to a known good state before ReadyToBoot event and after every SPI flash access (e.g. for MRC cache) has been finished in order to enable the OS to use SPI controller without constraints. Change-Id: I0a66344cd44e036c3999ae98d539072299cf5112 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15547 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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