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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-08-17 11:49:27 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-25 18:06:25 +0000
commit4f6e341e88e94e81087a1538b3364dcd47641c7f (patch)
tree31f663abad816df9d4b7d9733d1773d34c78a35d /util/hugo
parent639bf8a4bd977ec6b44ee008cadcffca85ae61e2 (diff)
soc/intel/common: Add function to DLOCK PR registers
Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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