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authorEricKY Cheng <ericky_cheng@compal.corp-partner.google.com>2022-11-19 01:50:57 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-11-23 14:00:06 +0000
commit9a41333c6bb68a1ebb5cf9d2a0d21257124a735e (patch)
tree5a31902f8e5c8ab1cc9ecc210b0a7babc9081eb1 /util/fuzz-tests
parent6a22c5f8ee5b9883f0a99d786491d6d70eb167d7 (diff)
mb/google/skyrim/var/winterhold: Add Vrm setting for SMT
All parameters of DPTC_INPUT() need to be configured on devicetree when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without configurations on devicetree would be 0 when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document #57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA and vrm_soc_current_limit_mA on devicetree with thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoidany thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:258572474, b:248976976, b:259167917, b:257394883 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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