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authorMondrian Nuessle <nuessle@uni-hd.de>2009-03-30 13:20:01 +0000
committerPeter Stuge <peter@stuge.se>2009-03-30 13:20:01 +0000
commit0f0f9bb9a2e1c1257fdfee0b50061e82ea92161b (patch)
tree6be2bb19f0e8eea5a086a5366f0bcf575dd6a048 /util/flashrom
parent3a8565a77bbf8f41c2c5560fb2c195c71949fc8c (diff)
flashrom: Board enable support for HP DL145 G3.
This is a BCM5785 based machine, WP# and TLB# need to be deasserted using GPIO 2 and 5 from the PM registers of the southbridge. This is very similar to the x3455 implementation. Signed-off-by: Mondrian Nuessle <nuessle@uni-hd.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom')
-rw-r--r--util/flashrom/board_enable.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/util/flashrom/board_enable.c b/util/flashrom/board_enable.c
index fc30b78866..00af1e87da 100644
--- a/util/flashrom/board_enable.c
+++ b/util/flashrom/board_enable.c
@@ -329,6 +329,19 @@ static int board_ibm_x3455(const char *name)
return 0;
}
+static int board_hp_dl145_g3_enable(const char *name)
+{
+ uint8_t byte;
+
+ /* Set GPIO lines in the Broadcom HT-1000 southbridge. */
+ OUTB(0x44, 0xcd6); /* GPIO 0 reg from PM regs */
+ byte = INB(0xcd7);
+ /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
+ OUTB(byte | 0x24, 0xcd7);
+
+ return 0;
+}
+
/**
* Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
*/
@@ -1014,6 +1027,20 @@ struct board_pciid_enable board_pciid_enables[] = {
.enable = ich6_gpio19_raise,
},
{
+ .first_vendor = 0x1166,
+ .first_device = 0x0223,
+ .first_card_vendor = 0x103c,
+ .first_card_device = 0x320d,
+ .second_vendor = 0x102b,
+ .second_device = 0x0522,
+ .second_card_vendor = 0x103c,
+ .second_card_device = 0x31fa,
+ .lb_vendor = "hp",
+ .lb_part = "dl145_g3",
+ .name = "HP DL145 G3",
+ .enable = board_hp_dl145_g3_enable,
+ },
+ {
.first_vendor = 0,
.first_device = 0,
.first_card_vendor = 0,