diff options
author | Jason Wang <Qingpei.Wang@amd.com> | 2008-11-28 21:36:51 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-11-28 21:36:51 +0000 |
commit | f22ce41840ae966a6f465e90c8f05aed9ae5ef6b (patch) | |
tree | 8cdef566a6d0c3449ab8f12adad0f05e5c6bd4ab /util/flashrom/spi.c | |
parent | 4ed326be5d7dec9ee16190847ea0b9f42117fe1a (diff) |
Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/spi.c')
-rw-r--r-- | util/flashrom/spi.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/util/flashrom/spi.c b/util/flashrom/spi.c index 8812eff123..b31a6b875f 100644 --- a/util/flashrom/spi.c +++ b/util/flashrom/spi.c @@ -42,6 +42,8 @@ int spi_command(unsigned int writecnt, unsigned int readcnt, case BUS_TYPE_ICH9_SPI: case BUS_TYPE_VIA_SPI: return ich_spi_command(writecnt, readcnt, writearr, readarr); + case BUS_TYPE_SB600_SPI: + return sb600_spi_command(writecnt, readcnt, writearr, readarr); default: printf_debug ("%s called, but no SPI chipset/strapping detected\n", @@ -157,6 +159,7 @@ int probe_spi_rdid4(struct flashchip *flash) case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: case BUS_TYPE_VIA_SPI: + case BUS_TYPE_SB600_SPI: return probe_spi_rdid_generic(flash, 4); default: printf_debug("4b ID not supported on this SPI controller\n"); @@ -229,7 +232,13 @@ uint8_t spi_read_status_register() unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ - spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + if (flashbus == BUS_TYPE_SB600_SPI) { + /* SB600 uses a different way to read status register. */ + return sb600_read_status_register(); + } else { + spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + } + return readarr[0]; } @@ -464,6 +473,14 @@ int spi_sector_erase(const struct flashchip *flash, unsigned long addr) return 0; } +int spi_write_status_enable() +{ + const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; + + /* Send EWSR (Enable Write Status Register). */ + return spi_command(JEDEC_EWSR_OUTSIZE, JEDEC_EWSR_INSIZE, cmd, NULL); +} + /* * This is according the SST25VF016 datasheet, who knows it is more * generic that this... @@ -500,9 +517,9 @@ int spi_disable_blockprotect(void) /* If there is block protection in effect, unprotect it first. */ if ((status & 0x3c) != 0) { printf_debug("Some block protection in effect, disabling\n"); - result = spi_write_enable(); + result = spi_write_status_enable(); if (result) { - printf_debug("spi_write_enable failed\n"); + printf_debug("spi_write_status_enable failed\n"); return result; } result = spi_write_status_register(status & ~0x3c); @@ -532,6 +549,8 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf) switch (flashbus) { case BUS_TYPE_IT87XX_SPI: return it8716f_spi_chip_read(flash, buf); + case BUS_TYPE_SB600_SPI: + return sb600_spi_read(flash, buf); case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: case BUS_TYPE_VIA_SPI: @@ -550,6 +569,8 @@ int spi_chip_write(struct flashchip *flash, uint8_t *buf) switch (flashbus) { case BUS_TYPE_IT87XX_SPI: return it8716f_spi_chip_write(flash, buf); + case BUS_TYPE_SB600_SPI: + return sb600_spi_write(flash, buf); case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: case BUS_TYPE_VIA_SPI: |