diff options
| author | Peter Stuge <peter@stuge.se> | 2009-01-26 03:37:40 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2009-01-26 03:37:40 +0000 |
| commit | c800eeb39bda2dbc33187af81d75651b1a9adf14 (patch) | |
| tree | dfb452628ecba9300c05ab15ac68fb3a86c48652 /util/flashrom/spi.c | |
| parent | 9ee44151cc9b0db006ba23999652e592e88d4708 (diff) | |
flashrom: SST25VF040B using 0x90 identification and AAI write.
SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.
From July 2008.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/spi.c')
| -rw-r--r-- | util/flashrom/spi.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/util/flashrom/spi.c b/util/flashrom/spi.c index 756fbe5602..57f4b133da 100644 --- a/util/flashrom/spi.c +++ b/util/flashrom/spi.c @@ -615,3 +615,29 @@ int spi_chip_write(struct flashchip *flash, uint8_t *buf) return 1; } + +int spi_aai_write(struct flashchip *flash, uint8_t *buf) { + uint32_t pos = 2, size = flash->total_size * 1024; + unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; + switch (flashbus) { + case BUS_TYPE_WBSIO_SPI: + fprintf(stderr, "%s: impossible with Winbond SPI masters, degrading to byte program\n", __func__); + return spi_chip_write(flash, buf); + default: + break; + } + flash->erase(flash); + spi_write_enable(); + spi_command(6, 0, w, NULL); + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + while (pos < size) { + w[1] = buf[pos++]; + w[2] = buf[pos++]; + spi_command(3, 0, w, NULL); + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + } + spi_write_disable(); + return 0; +} |