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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-05-13 14:58:23 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-05-13 14:58:23 +0000
commit967214d55974ef5b12a799f583d585bbd8b1c9b4 (patch)
treea8e35b61cab97706de194f6b93bde6b6a619be99 /util/flashrom/spi.c
parenta2e7c48d381e54be759429b0cbbfb5c0feaf0587 (diff)
flashrom: Move the SPI #defines from spi.c to spi.h
This patch has no code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/spi.c')
-rw-r--r--util/flashrom/spi.c61
1 files changed, 1 insertions, 60 deletions
diff --git a/util/flashrom/spi.c b/util/flashrom/spi.c
index cf547c58a7..cba6942209 100644
--- a/util/flashrom/spi.c
+++ b/util/flashrom/spi.c
@@ -27,70 +27,11 @@
#include <stdint.h>
#include <string.h>
#include "flash.h"
+#include "spi.h"
#define ITE_SUPERIO_PORT1 0x2e
#define ITE_SUPERIO_PORT2 0x4e
-/* Read Electronic ID */
-#define JEDEC_RDID 0x9f
-#define JEDEC_RDID_OUTSIZE 0x01
-#define JEDEC_RDID_INSIZE 0x03
-
-/* Write Enable */
-#define JEDEC_WREN 0x06
-#define JEDEC_WREN_OUTSIZE 0x01
-#define JEDEC_WREN_INSIZE 0x00
-
-/* Write Disable */
-#define JEDEC_WRDI 0x04
-#define JEDEC_WRDI_OUTSIZE 0x01
-#define JEDEC_WRDI_INSIZE 0x00
-
-/* Chip Erase 0x60 is supported by Macronix/SST chips. */
-#define JEDEC_CE_60 0x60
-#define JEDEC_CE_60_OUTSIZE 0x01
-#define JEDEC_CE_60_INSIZE 0x00
-
-/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */
-#define JEDEC_CE_C7 0xc7
-#define JEDEC_CE_C7_OUTSIZE 0x01
-#define JEDEC_CE_C7_INSIZE 0x00
-
-/* Block Erase 0x52 is supported by SST chips. */
-#define JEDEC_BE_52 0x52
-#define JEDEC_BE_52_OUTSIZE 0x04
-#define JEDEC_BE_52_INSIZE 0x00
-
-/* Block Erase 0xd8 is supported by EON/Macronix chips. */
-#define JEDEC_BE_D8 0xd8
-#define JEDEC_BE_D8_OUTSIZE 0x04
-#define JEDEC_BE_D8_INSIZE 0x00
-
-/* Sector Erase 0x20 is supported by Macronix/SST chips. */
-#define JEDEC_SE 0x20
-#define JEDEC_SE_OUTSIZE 0x04
-#define JEDEC_SE_INSIZE 0x00
-
-/* Read Status Register */
-#define JEDEC_RDSR 0x05
-#define JEDEC_RDSR_OUTSIZE 0x01
-#define JEDEC_RDSR_INSIZE 0x01
-#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
-
-/* Write Status Register */
-#define JEDEC_WRSR 0x01
-#define JEDEC_WRSR_OUTSIZE 0x02
-#define JEDEC_WRSR_INSIZE 0x00
-
-/* Read the memory */
-#define JEDEC_READ 0x03
-#define JEDEC_READ_OUTSIZE 0x04
-/* JEDEC_READ_INSIZE : any length */
-
-/* Write memory byte */
-#define JEDEC_BYTE_PROGRAM 0x02
-#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
-#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
uint16_t it8716f_flashport = 0;
/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */