Add more infrastructure for flashrom ICH9 support.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 42 insertions, 25 deletions

diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c
index 973fb81514..3dec881ed1 100644
--- a/util/flashrom/chipset_enable.c
+++ b/util/flashrom/chipset_enable.c
@@ -185,33 +185,37 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
 	return enable_flash_ich(dev, name, 0xdc);
 }
 
-static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name)
+void *ich_spibar = NULL;
+
+static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar)
 {
 	uint8_t old, new, bbs;
 	uint32_t tmp, gcs;
-	void *rcba;
+	void *rcrb;
 
-	/* Root Complex Base Address Register (RCBA) */
+	/* Read the Root Complex Base Address Register (RCBA) */
 	tmp = pci_read_long(dev, 0xf0);
+	/* Calculate the Root Complex Register Block address */
 	tmp &= 0xffffc000;
-	printf_debug("Root Complex Base Address Register = 0x%x\n", tmp);
-	rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp);
-	if (rcba == MAP_FAILED) {
+	printf_debug("Root Complex Register Block address = 0x%x\n", tmp);
+	rcrb = mmap(0, 0x4000, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp);
+	if (rcrb == MAP_FAILED) {
 		perror("Can't mmap memory using " MEM_DEV);
 		exit(1);
 	}
 	printf_debug("GCS address = 0x%x\n", tmp + 0x3410);
-	gcs = *(volatile uint32_t *)(rcba + 0x3410);
+	gcs = *(volatile uint32_t *)(rcrb + 0x3410);
 	printf_debug("GCS = 0x%x: ", gcs);
 	printf_debug("BIOS Interface Lock-Down: %sabled, ",
 		     (gcs & 0x1) ? "en" : "dis");
 	bbs = (gcs >> 10) & 0x3;
 	printf_debug("BOOT BIOS Straps: 0x%x (%s)\n",	bbs,
 		     (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
-	/* SPIBAR is at RCBA+0x3020 for ICH[78] and RCBA+0x3800 for ICH9. */
-	/* printf_debug("SPIBAR = 0x%x\n", tmp + 0x3020); */
+
+	/* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
+	printf_debug("SPIBAR = 0x%lx\n", tmp + spibar);
 	/* TODO: Dump the SPI config regs */
-	munmap(rcba, 0x3510);
+	ich_spibar =  rcrb + spibar;
 
 	old = pci_read_byte(dev, 0xdc);
 	printf_debug("SPI Read Configuration: ");
@@ -230,6 +234,19 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name)
 	return enable_flash_ich_dc(dev, name);
 }
 
+static int enable_flash_ich78(struct pci_dev *dev, const char *name)
+{
+	return enable_flash_ich_dc_spi(dev, name, 0x3020);
+}
+
+int ich9_detected = 0;
+
+static int enable_flash_ich9(struct pci_dev *dev, const char *name)
+{
+	ich9_detected = 1;
+	return enable_flash_ich_dc_spi(dev, name, 0x3800);
+}
+
 static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
 {
 	uint8_t val;
@@ -580,21 +597,21 @@ static const FLASH_ENABLE enables[] = {
 	{0x8086, 0x25a1, "Intel 6300ESB",	enable_flash_ich_4e},
 	{0x8086, 0x2640, "Intel ICH6/ICH6R",	enable_flash_ich_dc},
 	{0x8086, 0x2641, "Intel ICH6-M",	enable_flash_ich_dc},
-	{0x8086, 0x27b0, "Intel ICH7DH",	enable_flash_ich_dc_spi},
-	{0x8086, 0x27b8, "Intel ICH7/ICH7R",	enable_flash_ich_dc_spi},
-	{0x8086, 0x27b9, "Intel ICH7M",		enable_flash_ich_dc_spi},
-	{0x8086, 0x27bd, "Intel ICH7MDH",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2810, "Intel ICH8/ICH8R",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2811, "Intel ICH8M-E",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2812, "Intel ICH8DH",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2814, "Intel ICH8DO",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2815, "Intel ICH8M",		enable_flash_ich_dc_spi},
-	{0x8086, 0x2912, "Intel ICH9DH",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2914, "Intel ICH9DO",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2916, "Intel ICH9R",		enable_flash_ich_dc_spi},
-	{0x8086, 0x2917, "Intel ICH9M-E",	enable_flash_ich_dc_spi},
-	{0x8086, 0x2918, "Intel ICH9",		enable_flash_ich_dc_spi},
-	{0x8086, 0x2919, "Intel ICH9M",		enable_flash_ich_dc_spi},
+	{0x8086, 0x27b0, "Intel ICH7DH",	enable_flash_ich78},
+	{0x8086, 0x27b8, "Intel ICH7/ICH7R",	enable_flash_ich78},
+	{0x8086, 0x27b9, "Intel ICH7M",		enable_flash_ich78},
+	{0x8086, 0x27bd, "Intel ICH7MDH",	enable_flash_ich78},
+	{0x8086, 0x2810, "Intel ICH8/ICH8R",	enable_flash_ich78},
+	{0x8086, 0x2811, "Intel ICH8M-E",	enable_flash_ich78},
+	{0x8086, 0x2812, "Intel ICH8DH",	enable_flash_ich78},
+	{0x8086, 0x2814, "Intel ICH8DO",	enable_flash_ich78},
+	{0x8086, 0x2815, "Intel ICH8M",		enable_flash_ich78},
+	{0x8086, 0x2912, "Intel ICH9DH",	enable_flash_ich9},
+	{0x8086, 0x2914, "Intel ICH9DO",	enable_flash_ich9},
+	{0x8086, 0x2916, "Intel ICH9R",		enable_flash_ich9},
+	{0x8086, 0x2917, "Intel ICH9M-E",	enable_flash_ich9},
+	{0x8086, 0x2918, "Intel ICH9",		enable_flash_ich9},
+	{0x8086, 0x2919, "Intel ICH9M",		enable_flash_ich9},
 	{0x1106, 0x8231, "VIA VT8231",		enable_flash_vt823x},
 	{0x1106, 0x3177, "VIA VT8235",		enable_flash_vt823x},
 	{0x1106, 0x3227, "VIA VT8237",		enable_flash_vt823x},