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author | Urja Rannikko <urjaman@gmail.com> | 2008-10-23 23:33:18 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-10-23 23:33:18 +0000 |
commit | 38204a2c181b71d5c74a5bd9cfac14f450076ec2 (patch) | |
tree | ca48c9493a5d797597622f6f4da883f5b5a18aee /util/flashrom/chipset_enable.c | |
parent | c4f294f33f24b92d03e2663b954fd8426925c18b (diff) |
Add support for the ITE IT8661F/IT8770F, IT8673F, and IT8671F/IT8687R.
They all use a different init sequence than the more modern ITE Super I/Os.
For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be
valid. Contrary to other Super I/Os, the config port for these is _not_
hardcoded via hardware, instead it can be programmed by software, i.e.
you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd.
Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/chipset_enable.c')
0 files changed, 0 insertions, 0 deletions