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author | Aamir Bohra <aamir.bohra@intel.com> | 2018-10-17 11:55:01 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:20:54 +0000 |
commit | 3ee54bbf9413b5e174e65eff14769bdd2f5a3203 (patch) | |
tree | 1c27e4e0434d3e22e4fb9bb38ba59aa623070f80 /util/exynos | |
parent | bb7f4c7a4f3a076ba3e52fea9228e4a064316128 (diff) |
soc/intel/icelake: Do initial SoC commit
Clone entirely from Cannonlake
commit id: 3487095304dbbbf66de86f8bce0e40b7acb3ea27
List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
5.a. All NHLT blobs and related files.
5.b. remove cnl_memcfg_init.c file, will be added later.
5.c. Remove vr_config.c, this is WIP.
5.d. Clean up upd override in fsp_params.c,
will be added once FSP available.
5.e Remove CNL-H based GPIO configuartion.
Ice Lake specific changes will follow in subsequent patches.
Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/exynos')
0 files changed, 0 insertions, 0 deletions