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authorTobias Diedrich <ranma+coreboot@tdiedrich.de>2010-11-29 20:40:33 +0000
committerTobias Diedrich <ranma@tdiedrich.de>2010-11-29 20:40:33 +0000
commitca6d8084dde1e60cb0bef3bf6cb502a95efbf965 (patch)
tree1471a2e267949b453efab213462ea262d7fbc145 /util/ectool/ectool.c
parentb97030d706987a466751eac9c29d9f26e68a9683 (diff)
Tobias Diedrich wrote:
> Stefan Reinauer wrote: > > The specified IO port is most likely wrong. As the comment mentions, the > > SSDT is a good place for that. A preprocessor define used both in the > > CPU init code and in the asl would solve the problem without an SSDT. > > For some info on CPU SSDT creation on intel check out > > src/cpu/intel/speedstep/acpi.c > > The IO port is ok (and I wrote the comment myself ;)): > DEFAULT_PMBASE is 0xe400 > PCNTRL reg offset is 0x10 > > Using the preprocessor will probably work too if iasl can do simple > arithmetic (likely yes), I'll look into that. BTW, my first idea was to use an acpi method that looks up pmbase in the pci cfg space, but when I define a method like this: Method(TEST, 2) { Return (Add(Arg0, Arg1)) } I get: |build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0, |0x01, TEST(0xe400, 0x10), 0x06) {} |Error 4096 - syntax error, unexpected PARSEOP_NAMESEG, |expecting ')' ^ While using the builtin Add() directly works. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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