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authorKevin L Lee <kevin.l.lee@intel.com>2014-12-12 14:02:43 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-10 20:06:59 +0200
commit5c8d43e207b4349e95ffb359e0ed08ffa3f789a0 (patch)
tree1c6ab16fa1429d87cde744844f4613b917154677 /util/dumpmmcr
parente6cf3c6f78149b4c11c7a53f27e684bd560c0ac2 (diff)
baytrail: fix the coding error on PCIe L1 exit latency
The original code uses L1EXIT_MASK to shift the bit for PCIe L1 exit latency, the code should use L1EXIT_SHIFT for bit shifting. BUG=chrome-os-partner:34037 BRANCH=None TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15] set to 010b. Correspond WIFI device performance got improvement. Signed-off-by: Kevin L Lee <kevin.l.lee@intel.com> Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92 Original-Reviewed-on: https://chromium-review.googlesource.com/234673 Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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