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authorRobert Chen <robert.chen@quanta.corp-partner.google.com>2022-02-21 19:32:39 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-02-24 00:32:24 +0000
commite39d371909ff6ac6968b63cfc945338212c9a1c4 (patch)
treee99457b5650ddfddb222579ae90711dc1cab2c73 /util/dtd_parser/dtd_parser.py
parent77711b86778bd31acd866bfbc979ebab3708399a (diff)
mb/google/brya/var/vell: Corrects ACPI _PLD macro setting
This patch is to denote the correct side of ACPI _PLD usb C ports. +-------------------------+ | LCD | | | | | +-------------------------+ PORT_C2 | | PORT_C1 PORT_C3 | DB MB | PORT_C0 | | +-------------------------+ BUG=b:220634230 TEST=emerge-brya coreboot Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/dtd_parser/dtd_parser.py')
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