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authorMaximilian Schander <coreboot@mimoja.de>2017-11-05 06:14:55 +0100
committerNico Huber <nico.h@gmx.de>2017-11-08 11:42:26 +0000
commit798564333d541ab29abe210f818a500a7582baf7 (patch)
treeefbcd731328970b557facdb9af1ce9fce47f73ff /util/docker/Makefile
parent98c11ddc9e95f15a8c10b212e9bfc1180dc83369 (diff)
util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake
Both registers behave the same as on the previous generation Taken from * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2 * Page 55 and 62 * 332688-003EN Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9 Signed-off-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/22350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
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