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authorFelix Held <felix-coreboot@felixheld.de>2020-12-11 15:55:45 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-18 17:20:56 +0000
commit07462ef3d69e4458110bf27a1ecb1d4379929ff4 (patch)
treebf657ee843f1b84cfe91b680b1b1f7536b43761b /util/crossgcc
parent02a5dddb01a6629aaf64fdc196b996883602a293 (diff)
soc/amd/cezanne: add GPIO support
This still uses the common GPIO code that supports setting up SMI/SCI support for the GPIOs in all stages, which will get removed in future patches, so for now the SoC's gpio.c needs to be included in all stages. Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/crossgcc')
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