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author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2012-10-26 19:02:44 +0200 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-10-26 21:55:38 +0200 |
commit | 95c607feadf6325c90842fec8fa64a2b32208295 (patch) | |
tree | 88b8a7373fb8dc6be8c616b46081c49b00f8caaf /util/crossgcc | |
parent | 3e9155dddf4a439703f7b762648eb820307dbfe4 (diff) |
iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
The PCI registers should be accessed aligned and 0x62 is not 32bit
aligned therefore this patch changes it to a 16bit access.
Change-Id: I00725a4569f471eedb061834f626911b42e734fb
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1631
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'util/crossgcc')
0 files changed, 0 insertions, 0 deletions