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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 09:42:47 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:18:13 +0000 |
| commit | b30d0545843b6ba3e8c0976a1fc0f1413be1608b (patch) | |
| tree | 41c27030e6e7521a3839cddf19b6d375a535f71f /util/crossgcc | |
| parent | a15eaec1e6975d78687aaea06996464b5a67f14c (diff) | |
soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'util/crossgcc')
0 files changed, 0 insertions, 0 deletions