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| author | Xiang Wang <wxjstz@126.com> | 2019-06-21 13:04:10 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-03-09 23:34:25 +0000 |
| commit | 52b81845de44dfa1af50e203c2cab9a953a628f1 (patch) | |
| tree | d7345f8fcb0d1f857affd2d5dc310ed2715bdd29 /util/crossgcc/sum | |
| parent | 5787a4c53b56325dad364f11774b481fc27a9684 (diff) | |
arch/riscv: Add SMP support for exception handler
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68841
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'util/crossgcc/sum')
0 files changed, 0 insertions, 0 deletions