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author | Furquan Shaikh <furquan@google.com> | 2020-11-28 19:47:41 -0800 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-12-02 21:53:17 +0000 |
commit | 4a1cbdd51aafa671ecb6c93a475ca9bf6f9ca914 (patch) | |
tree | 094ac01d6905b40a6d094bd430b2b697b662e5e5 /util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum | |
parent | a5a529599d264da5890fad7b678f7ff9e5e47a80 (diff) |
soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
This change drops the special check added for TGL/JSL platforms and
performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later
in the boot process to ensure that the memory training parameters are
written back to SPI flash before performing a reset for CSE RW
jump. With the recent changes in CB:44196 ("mrc_cache: Update
mrc_cache data in romstage"), MRC cache is updated right away in
romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I947a40cd9776342d2067c9d5a366358917466d58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Diffstat (limited to 'util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum')
0 files changed, 0 insertions, 0 deletions