diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-02-03 15:20:04 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-28 16:01:15 +0000 |
| commit | 2d22f82a0c3a23a023051126aedb65c57d3fce2f (patch) | |
| tree | dafba70ada79d42dab9c0ec45fe07a6df9c34a63 /util/crossgcc/patches | |
| parent | fb670fee3c8729a3b64f1fc171eb59073774029a (diff) | |
mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configuration
List of changes:
1. Add correct board Id for ADL-M LP5 configuration
2. Add spd hex files for LP5 Micron part
3. Update memory.c file with correct Dq-dqs and byte mapping for LP5
BUG=None
BRANCH=None
TEST=Build is successful for ADL-M RVP
Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'util/crossgcc/patches')
0 files changed, 0 insertions, 0 deletions