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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-28 20:26:34 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-06 16:09:03 +0000 |
| commit | 921fa84f9e6802b28dd42cb905c396d033e64836 (patch) | |
| tree | e4d5c99ad5a32cb1fd109e6626e7c1576398454d /util/crossgcc/getopt.c | |
| parent | ad282592b450c6309abe829f3c4e0d2b0111fb31 (diff) | |
inteltool: Fix displaying 64bit spi registers
The registers were taken from the wrong addess since the spibar offset
was not added to it.
This also fixes the endianness.
Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/crossgcc/getopt.c')
0 files changed, 0 insertions, 0 deletions