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author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-14 10:23:19 -0600 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2020-05-26 20:51:32 +0000 |
commit | e184e39e2ed9ac3f76d2c4f2cc830e335a216e45 (patch) | |
tree | e4388384481781e0d55bc82e8c4c1bd9b3e286cb /util/crossgcc/Makefile | |
parent | 7f00dba33beb65e0380ed4b3194102083630b2f4 (diff) |
drivers/intel/pmc_mux/con: Add new PMC MUX & CON chip drivers
The Tiger Lake PMC device has a MUX device which is expected to be
exposed in ACPI tables. The MUX device simply has a _HID and _DDN.
The CON devices link the USB-2 and USB-3 port numbers (from SoC
point of view) to the physical connector. They also have orientation
options for the sideband (SBU) and USB High Speed signals (HSL),
meaning that they can be fixed (i.e, another device besides the SoC
controls the orientation, and effectively the SoC is following only
CC1 or CC2 orientation), or they can follow the CC lines.
BUG=b:151646486
TEST=Tested with next patch in series (see TEST line there)
Change-Id: I8b5f275907601960410459aa669e257b80ff3dc2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'util/crossgcc/Makefile')
0 files changed, 0 insertions, 0 deletions